In many conventional memory systems, such as dynamic random access memory (DRAM), binary digits (bits) are stored in memory cells, and are accessed by a processor that specifies a linear address that is associated with the given cell. This system provides rapid access to any portion of the memory system. Within the field of DRAM, there exist two well-known architectures for arranging the memory cells and bitlines, each of which provides distinct advantages and disadvantages.
The first architecture is the open bitline architecture, generally shown in FIGS. 1A and 1B. The arrangement shown in FIG. 1A is representative of the physical layout of the memory cells, bitlines and wordlines with respect to the bitline sense amplifier on a fabricated device. Some circuitry is intentionally omitted to simplify the schematic. It should be understood by those skilled in the art that wordlines would run perpendicular to the bitlines, memory cells would be located near the intersection between each wordline and bitline, and read/write circuits are coupled to the bitlines. Complementary bitlines 32 and 34 extend away from the left and right sides of the bitline sense amplifier 33 into memory arrays 20 and 22 respectively. A bitline sense amplifier such as sense amplifier 33 is well known in the art and typically includes a cross-coupled complementary pair of CMOS transistors. An n-channel equalization transistor (not shown) is connected between bitlines 32 and 34 for electrically shorting the two bitlines together, and has a gate controlled by a bitline equalization signal BLEQ. Bitlines 32 and 34, equalization transistor and sense amplifier 33 form one open bitline pair. Another bitline pair consisting of bitlines 36 and 37, an equalization transistor (not shown) and sense amplifier 38 are configured identically to their corresponding elements from the first open bitline pair. In a memory device, a plurality of open bitline pairs are arranged one below the other as shown in FIG. 1A, in which all the bitlines connected to the left side of the sense amplifiers 33 are part of the left array 20 and all the bitlines connected to the right side of the sense amplifiers 33 are part of the right array 22. For DRAM memories, it is necessary to precharge bitlines prior to reading the stored data, through bitline precharge transistors (not shown), to a mid-point potential level VBL, prior to reading data from a DRAM memory cell connected to it. This mid-point potential level is typically half the high power supply potential used by the bitline sense amplifiers. This is to allow the bitline sense amplifier to detect small changes in the potential level of the bitline when charge is added or removed by the memory cell storage capacitor. The bitlines may alternatively be precharged to the potential level VBL by coupling them to a voltage supply calibrated to the desired potential VBL.
A read and precharge operation for the open bitline architecture of FIG. 1A will briefly be described. It is assumed that all bitlines have been precharged to a mid-point potential level VBL between a high and a low logic potential level in a previous operation. During a read operation, one wordline of either the left or right array is driven to access one memory cell connected to each bitline of the respective array. The bitlines of the unaccessed array remain at the mid-point potential level, which is the reference potential level used by the sense amplifier during sensing of the data on the bitlines of the accessed array. Alternatively, both arrays 20, 22 contain complementary data, in which case corresponding wordlines of both arrays 20, 22 are driven, and the potential of each pair of complementary bitlines changes in opposite directions, thereby increasing the shift in potential to be detected by the sense amplifier. The sense amplifier detects the shift in the potential level of the bitline when the storage capacitor of the accessed memory cell is coupled to the bitline, and amplifies and latches the full CMOS logic potential level of the bitline. Since sense amplifier is a cross-coupled latch circuit, the accessed bitline and its corresponding complementary bitline are driven to opposite logic potential levels after the data has been read out, and since the selected wordline remains activated, the full CMOS level is restored into each accessed cell. The bitlines are then precharged again in preparation for the next read operation.
The open bitline architecture allows for efficient packing of DRAM cells in a 6F2 cell design to reduce the overall area occupied by the memory array, as can be seen in FIG. 1B. However, when all of the bitlines of an array are sensed concurrently in a single read operation, the capacitative coupling between adjacent bitlines can generate crosstalk noise, particularly between adjacent bitlines sensing opposite potentials. This crosstalk can manifest itself, for example, if the rising potential on a bitline pulls up the falling potential on an adjacent bitline or vice versa, thereby interfering with the ability of the sense amplifier to quickly and accurately detect the bit to be read, resulting in increased access time and potential read errors. These errors can be mitigated to some extent by manufacturing the DRAM cells with larger capacitors capable of storing more charge. However, this has its own disadvantages, including increased power consumption and limiting the reduction in size of the DRAM array. Another disadvantage of the open bitline architecture is that each sense amplifier must fit within a two-bitline pitch, which can make the layout of the overall device challenging.
The second architecture is the folded bitline architecture, generally shown in FIGS. 2A and 2B. The arrangement shown in FIG. 2A is representative of the physical layout of the cells, bitlines and wordlines with respect to the bitline sense amplifier on a fabricated device. Some circuitry is intentionally omitted to simplify the schematic. It should be understood by those skilled in the art that wordlines would run perpendicular to the bitlines, memory cells would be located near the intersection between each wordline and bitline, and read/write circuits are coupled to the bitlines. Complementary bitlines 46 and 47 extend away from the left side of a shared bitline sense amplifier 41 into memory array 50, and complementary bitlines 48 and 49 extend away from the right side of sense amplifier 41 into memory array 52. A shared bitline sense amplifier such as sense amplifier 41 is well known in the art, and would typically consist of a pair of cross-coupled complementary pair of CMOS transistors. N-channel equalization transistors (not shown) are connected between bitlines 46 and 47 at opposite ends of bitlines 46 and 47. Similarly, n-channel equalization transistors (not shown) are connected between bitlines 48 and 49 at opposite ends of bitlines 48 and 49. Equalization transistors (not shown) for the left memory array 50 have gates controlled by a left array bitline equalization signal BLEQ_L, and equalization transistors (not shown) for the right memory array 52 have gates controlled by a right array bitline equalization signal BLEQ_R. In a typical array, a shared sense amplifier and respective pairs of folded bitlines are arranged in a column, and several columns can be arranged side by side. In FIG. 2A, bitlines 46 and 47 and equalization transistors for the left array 50 are located within the left array 50, and bitlines 48 and 49 and equalization transistors for the right array 52 are located within the right array 52. The bitlines are precharged prior to reading the stored data, in a manner similar to the open bitline architecture.
A read and precharge operation for the folded bitline architecture of FIG. 2A will briefly be described. It is assumed that all bitlines have been precharged to a mid-point potential level VBL between a high and a low logic potential level in a previous operation. During a read operation, one wordline of either the left or right array is driven to access one memory cell connected each bitline, BL0 or BL0* for example, of the respective array, and the corresponding equalization control signal, BLEQ_L or BLEQ_R is turned off. The folded complementary bitlines of the unaccessed array, BL1 and BL1* for example, remain at the precharged mid-point potential level. If a memory cell connected to BL0 is accessed by the driven wordline, then the complementary bitline BL0* remains at the precharged mid-point potential level VBL, which is the reference potential level used by sense amplifier 41. Accordingly, the role of each bitline is reversed if a memory cell connected to BL0* is accessed instead of a memory cell connected to BL0. Furthermore, the roles of both folded bitline pairs is reversed if a driven wordline accesses a memory cell connected to either BL1 or BL1*.
Alternatively, the memory cells accessed by both bitlines BL0, BL0* contain complementary data, in which case corresponding wordlines of both complementary cells are driven, and the potential of each pair of complementary bitlines changes in opposite directions, thereby increasing the shift in potential to be detected by the sense amplifier. Since the sense amplifier is a cross-coupled latch circuit, the accessed bitline and its corresponding complementary bitline are driven to opposite logic potential levels after the data has been read out. The bitlines are then precharged again in preparation for the next read operation.
While the folded bitline architecture typically generates less noise than the open bitline architecture, and allows a four-bitline pitch for sense amplifiers, it has drawbacks of its own. In particular, the folded bitline architecture does not allow efficient packing of DRAM cells, typically requiring a larger 8F2 cell design as can be seen in FIG. 2B, as compared to the 6F2 open bitline layout of FIG. 1B.
Various arrangements have been proposed which combine features of the open and folded bitline architectures. These arrangements offer different levels of compromise between the advantages and disadvantages of both architectures. However, it is believed that further improvements are possible.
Therefore, there is a need to provide a dynamic memory array architecture which operates with reduced noise and is arranged with an efficient packing density to occupy small silicon area.
There is also a need to provide a dynamic memory array architecture with reduced power consumption.
There is also a need to provide an open bitline dynamic memory array architecture permitting a simplified arrangement of sense amplifiers.
There is also a need to provide a method of operating a dynamic memory array architecture having these characteristics.